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PIC32MX3XX/4XX
TABLE 7-1:
INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)
Interrupt Source (1)
IRQ
Vector
Number
Interrupt Bit Location
Highest Natural Order Priority
Flag
Enable
Priority
Subpriority
SPI2E – SPI2 Fault
SPI2TX – SPI2 Transfer Done
SPI2RX – SPI2 Receive Done
U2E – UART2 Error
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
I2C2B – I2C2 Bus Collision Event
I2C2S – I2C2 Slave Event
I2C2M – I2C2 Master Event
FSCM – Fail-Safe Clock Monitor
RTCC – Real-Time Clock and
37
38
39
40
41
42
43
44
45
46
47
31
31
31
32
32
32
33
33
33
34
35
IFS1<5>
IFS1<6>
IFS1<7>
IFS1<8>
IFS1<9>
IFS1<10>
IFS1<11>
IFS1<12>
IFS1<13>
IFS1<14>
IFS1<15>
IEC1<5>
IEC1<6>
IEC1<7>
IEC1<8>
IEC1<9>
IEC1<10>
IEC1<11>
IEC1<12>
IEC1<13>
IEC1<14>
IEC1<15>
IPC7<28:26>
IPC7<28:26>
IPC7<28:26>
IPC8<4:2>
IPC8<4:2>
IPC8<4:2>
IPC8<12:10>
IPC8<12:10>
IPC8<12:10>
IPC8<20:18>
IPC8<28:26>
IPC7<25:24>
IPC7<25:24>
IPC7<25:24>
IPC8<1:0>
IPC8<1:0>
IPC8<1:0>
IPC8<9:8>
IPC8<9:8>
IPC8<9:8>
IPC8<17:16>
IPC8<25:24>
Calendar
DMA0 – DMA Channel 0
DMA1 – DMA Channel 1
DMA2 – DMA Channel 2
DMA3 – DMA Channel 3
FCE – Flash Control Event
USB
48
49
50
51
56
57
36
37
38
39
44
45
IFS1<16>
IFS1<17>
IFS1<18>
IFS1<19>
IFS1<24>
IFS1<25>
IEC1<16>
IEC1<17>
IEC1<18>
IEC1<19>
IEC1<24>
IEC1<25>
IPC9<4:2>
IPC9<12:10>
IPC9<20:18>
IPC9<28:26>
IPC11<4:2>
IPC11<12:10>
IPC9<1:0>
IPC9<9:8>
IPC9<17:16>
IPC9<25:24>
IPC11<1:0>
IPC11<9:8>
Lowest Natural Order Priority
Note 1:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose –
Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals.
? 2010 Microchip Technology Inc.
DS61143G-page 91
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